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general description the MAX1144/max1145 are 150ksps, 14-bit adcs. these serially interfaced adcs connect directly to spi, qspi, and microwire devices without external logic. they combine an input scaling network, internal track/hold, clock, and three general-purpose digital output pins (for external multiplexer or pga con- trol) in a 20-pin ssop package. the excellent dynamic performance (thd 90db), high speed (150ksps in bipolar mode), and low power (8.0ma) of these adcs make them ideal for applications such as industrial process control, instrumentation, and medical applica- tions. the MAX1144 accepts input signals of 0 to +6v (unipo- lar) or ?v (bipolar), while the max1145 accepts input signals of 0 to +2.048v (unipolar) or ?.048v (bipolar). operating from a single 3.135v to 3.465v analog digital supply, powerdown modes reduce current consump- tion to 0.15ma at 10ksps and further reduce supply current to less than 20? slower data rates. a serial strobe output (sstrb) allows direct connection to the tms320 family digital-signal processors. the MAX1144/max1145 user can select either the internal clock or an external serial-interface clock for the adc to perform analog-to-digital conversions. the MAX1144/max1145 feature internal calibration cir- cuitry to correct linearity and offset errors. on-demand calibration allows the user to optimize performance. three user-programmable logic outputs are provided for the control of an 8-channel mux or pga. the MAX1144/max1145 are available in a 20-pin ssop package and are fully specified over the -40? to +85? temperature range. applications industrial process control industrial i/o modules data-acquisition systems medical instruments portable and battery-powered equipment features 150ksps (bipolar) and 125ksps (unipolar) sampling adc 14 bits, no missing codes 1lsb inl guaranteed -100db thd 3.3v single-supply operation low-power operation 5ma typ (unipolar mode) 1.2a shutdown mode software-configurable unipolar and bipolar input ranges 0 to +6v and 6v (MAX1144) 0 to +2.048v and 2.048v (max1145) internal or external clock spi/qspi/microwire tms320-compatible serial interface three user-programmable logic outputs small 20-pin ssop package MAX1144/max1145 14-bit adcs, 150ksps, 3.3v single supply ________________________________________________________________ maxim integrated products 1 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 ain agnd cref cs av dd agnd av dd ref top view din dv dd dgnd sclk p1 p2 shdn dgnd 12 11 9 10 rst dout sstrb po MAX1144 max1145 ssop pin configuration ordering information 19-2465; rev 0; 4/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information continued at end of data sheet. functional diagram and typical application circuit appear at end of data sheet. part temp range pin- package inl (lsb) MAX1144 acap 0 c to +70 c 20 ssop 1 MAX1144bcap 0 c to +70 c 20 ssop 2 MAX1144aeap -40 c to +85 c 20 ssop 1 MAX1144beap -40 c to +85 c 20 ssop 2 spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor, corp.
MAX1144/max1145 14-bit adcs, 150ksps, 3.3v single supply 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = dv dd = 3.3v 5%, f sclk = 3.6mhz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, v ref = 2.048v, c ref = 4.7f, c cref = 1f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd, dv dd to dgnd ..............................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v ain to agnd ....................................................................16.5v cref, ref to agnd ................................-0.3v to (av dd + 0.3v) digital inputs to dgnd.............................................-0.3v to +6v digital outputs to dgnd .........................-0.3v to (dv dd + 0.3v) continuous power dissipation (t a = +70 c) 20-pin ssop (derate 8.00mw/ c above +70 c) .........640mw operating temperature ranges max114_ _cap...................................................0 c to +70 c max114_ _eap ................................................-40 c to +85 c storage temperature range .............................-60 c to +150 c junction temperature ......................................................+150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units dc accuracy (note 1) resolution 14 bits max114_a 1 relative accuracy inl bipolar mode (note 2) max114_b 2 lsb no missing codes 14 bits max114_a -1 +1 differential nonlinearity dnl bipolar mode max114_b -1.00 +1.75 lsb transition noise 0.47 lsb rms unipolar 4 offset error bipolar 6 mv unipolar 0.2 gain error (note 3) bipolar 0.3 %fsr offset drift (bipolar and unipolar) excluding reference drift 1 ppm/ c gain drift (bipolar and unipolar) excluding reference drift 4 ppm/ c d yna m ic spec if ic a t io n s ( 5 k hz sine- wave in pu t, 1 50 k s ps , 3 .6m h z c l o ck , bipo la r in pu t m o de. m a x1 14 4 , 1 2 v p-p . m a x1 14 5 , 4 .09 6 v p-p .) f in = 5khz 78 82 signal-to-noise plus distortion (sinad) f in = 75khz 81 db f in = 5khz 78 82 signal-to-noise ratio (snr) f in = 75khz 81 db f in = 5khz -100 -90 total harmonic distortion (thd) f in = 75khz -94 db f in = 5khz 92 105 spurious-free-dynamic range (sfdr) f in = 75khz 98 db analog input unipolar 0 +6 MAX1144 bipolar -6 +6 unipolar 0 +2.048 input range max1145 bipolar -2.048 +2.048 v
MAX1144/max1145 14-bit adcs, 150ksps, 3.3v single supply _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = 3.3v 5%, f sclk = 3.6mhz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, v ref = 2.048v, c ref = 4.7f, c cref = 1f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units unipolar 7.5 10.5 MAX1144 bipolar 5.9 8.4 unipolar 100 1000 input impedance max1145 bipolar 3.4 5.3 k ? input capacitance 32 pf conversion rate internal clock frequency 3 mhz aperture delay t ad 10 ns aperture jitter t aj 50 ps mode 1 (24 external clock cycles per conversion) unipolar 0.1 3.0 external clock frequency f sclk bipolar 0.1 3.6 mhz unipolar 4.17 125 sample rate f s = f sclk / 24 bipolar 4.17 150 ksps unipolar 8 240 conversion time (note 4) t conv+acq = 24 / f sclk bipolar 6.7 240 s mode 2 (internal clock) external clock frequency (data transfer only) 4 mhz conversion time (sstrb low pulse width) 5.3 7 s unipolar 1.67 acquisition time (note 5) bipolar 1.39 s mode 3 (32 external clock cycles per conversion) external clock frequency f sclk unipolar or bipolar 0.1 3.6 mhz sample rate f s = f sclk / 32 unipolar or bipolar 3.125 112 ksps conversion time (note 4) t conv+acq = 32 / f sclk unipolar or bipolar 8.89 320 s external reference input range (notes 6, 7) 1.9 2.048 2.2 v v ref = 2.048v, f sclk = 3.6mhz 110 v ref = 2.048v, f sclk = 0 100 input current in power-down, f sclk = 0 0.1 a digital inputs input high voltage v ih 2.4 v input low voltage v il 0.8 v input leakage i in v in = 0 or dv dd -1 +1 a
MAX1144/max1145 14-bit adcs, 150ksps, 3.3v single supply 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units input hysteresis v hyst 0.2 v input capacitance c in 10 pf digital outputs output high voltage v oh i source = 0.5ma dv dd - 0.5 v i sink = 5ma 0.4 output low voltage v ol i sink = 16ma 0.8 v three-state leakage current i l cs = dv dd -10 +10 a three-state output capacitance cs = dv dd 10 pf power supplies analog supply av dd 3.135 3.3 3.465 v digital supply dv dd 3.135 3.3 3.465 v unipolar mode 3.9 8 bipolar mode 7 11 ma analog supply current i analog shdn = 0, or software power-down mode 0.1 10 a unipolar or bipolar mode 1 2 ma digital supply current i digital shdn = 0, or software power-down mode 1.1 10 a power-supply rejection ratio (note 8) psrr av dd = dv dd = 3.135v to 3.465v 65 db electrical characteristics (continued) (av dd = dv dd = 3.3v 5%, f sclk = 3.6mhz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, v ref = 2.048v, c ref = 4.7f, c cref = 1f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) timing characteristics (figures 5 and 6) (av dd = dv dd = 3.3v 5%, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units din to sclk setup t ds 50 ns din to sclk hold t dh 0ns sclk to dout valid t do 70 ns cs fall to dout enable t dv c load = 50pf 80 ns cs rise to dout disable t tr c load = 50pf 80 ns cs to sclk rise setup t css 100 ns cs to sclk rise hold t csh 0ns sclk high pulse width t ch 120 ns sclk low pulse width t cl 120 ns sclk fall to sstrb t sstrb c load = 50pf 80 ns cs fall to sstrb enable t sdv c load = 50pf, external clock mode 80 ns cs rise to sstrb disable t str c load = 50pf, external clock mode 80 ns sstrb rise to sclk rise t sck internal clock mode 0 ns rst pulse width t rs 278 70 ns
MAX1144/max1145 14-bit adcs, 150ksps, 3.3v single supply _______________________________________________________________________________________ 5 timing characteristics (figures 5 and 6) (continued) (av dd = dv dd = 3.3v 5%, t a = t min to t max , unless otherwise noted.) note 1: tested at av dd = dv dd = 3.3v, bipolar input mode. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nullified. note 3: offset nullified. note 4: conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. includes the acquisition time. note 5: acquisition time is 5 clock cycles in short acquisition mode and 13 clock cycles in long acquisition mode. note 6: performance is limited by the converter s noise floor, typically 300v p-p . note 7: when an external reference has a different voltage than the specified typical value, the full scale of the adc scales propor- tionally. note 8: defined as the change in positive full scale caused by a 5% variation in the nominal supply voltage. typical operating characteristics (MAX1144/max1145, av dd = dv dd = 3.3v, f sclk = 3.6mhz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, ref = 2.048v, 4.7f on ref, 1f on cref, t a = +25 c, unless otherwise noted.) integral nonlinearity vs. digital output code MAX1144/45 toc01 digital output code integral nonlinearity (lsb) 13649 11943 8531 10237 3413 5119 6825 1707 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 1 15355 differential nonlinearity vs. digital output code MAX1144/45 toc02 digital output code differential nonlinearity (lsb) 13649 11943 8531 10237 3413 5119 6825 1707 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 1 15355 total supply current vs. temperature MAX1144/45 toc03 temperature ( c) total supply current (ma) 80 60 20 40 0 -20 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9.0 8.0 -40 a: av dd , dv dd = 3.135v b: av dd , dv dd = 3.3v c: av dd , dv dd = 3.465v c b a
MAX1144/max1145 6 _______________________________________________________________________________________ typical operating characteristics (continued) (MAX1144/max1145, av dd = dv dd = 3.3v, f sclk = 3.6mhz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, ref = 2.048v, 4.7f on ref, 1f on cref, t a = +25 c, unless otherwise noted.) offset voltage vs. temperature MAX1144/45 toc04 temperature ( c) offset error (mv) 80 60 20 40 0 -20 -2.5 -2.0 -1.0 -0.5 0 -40 a: av dd , dv dd = 3.135v b: av dd , dv dd = 3.3v c: av dd , dv dd = 3.465v c b a -1.5 gain error vs. temperature MAX1144/45 toc05 temperature ( c) gain error (% full scale) 80 60 20 40 0 -20 0.01 0 0.03 0.02 0.04 0.05 0.06 -40 a: av dd , dv dd = 3.135v b: av dd , dv dd = 3.3v c: av dd , dv dd = 3.465v c b a total supply current vs. conversion rate (using shutdown) MAX1144/45 toc06 conversion rate (ksps) total supply current (ma) 1000 100 10 1 0.01 100 10 1 0.1 0 fft plot MAX1144/45 toc07 frequency (khz) amplitude (db) 60 50 40 30 20 10 -100 -80 -60 -40 -20 0 -120 070 f sample = 150khz f in = 5khz sinad plot MAX1144/45 toc08 frequency (khz) amplitude (db) 10 1 10 20 30 40 50 60 70 80 90 100 0 0.1 100 f sample = 150khz sfdr plot MAX1144/45 toc09 frequency (khz) amplitude (db) 10 1 10 20 30 40 50 60 70 80 90 100 110 120 0 0.1 100 f sample = 150khz thd plot MAX1144/45 toc10 frequency (khz) amplitude (db) 10 1 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 0.1 100 f sample = 150khz 14-bit adcs, 150ksps, 3.3v single supply
MAX1144/max1145 14-bit adcs, 150ksps, 3.3v single supply _______________________________________________________________________________________ 7 pin description pin name function 1 ref adc reference input. connect a 2.048v voltage source to ref. bypass ref to agnd with 4.7f capacitor. 2av dd analog supply. connect to pin 4. 3 agnd analog ground. this is the primary analog ground (star ground). 4av dd analog supply, 3.3v 5%. bypass av dd to agnd (pin 3) with a 0.1f capacitor. 5 dgnd digital ground 6 shdn shutdown control input. drive shdn low to put the adc in shutdown mode. 7 p2 user-programmable output 2 8 p1 user-programmable output 1 9 p0 user-programmable output 0 10 sstrb serial strobe output. in internal clock mode, sstrb goes low when the adc begins a conversion and goes high when the conversion is finished. in external clock mode, sstrb pulses high for one clock period before the msb decision. it is high impedance when cs is high in external clock mode. 11 dout serial data output. msb first, straight binary format for unipolar input, two s complement for bipolar input. each bit is clocked out of dout at the falling edge of sclk. 12 rst reset input. drive rst low to put the device in the power-on default mode. see the power-on reset section. 13 sclk serial data clock input. serial data on din is loaded on the rising edge of sclk, and serial data is updated on dout on the falling edge of sclk. in external clock mode sclk sets the conversion speed. 14 dgnd digital ground. connect to pin 5. 15 dv dd digital supply, 3.3v 5%. bypass dv dd to dgnd (pin 14) with a 0.1f capacitor. 16 din serial data input. serial data on din is latched on the rising edge of sclk. 17 cs chip select input. drive cs low to enable the serial interface. when cs is high dout is high impedance. in external clock mode sstrb is high impedance when cs is high. 18 cref reference buffer bypass. bypass cref to agnd (pin 3) with 1f. 19 agnd analog ground. connect to pin 3. 20 ain analog input
MAX1144/max1145 detailed description the MAX1144/max1145 adcs use a successive- approximation technique and input track/hold (t/h) cir- cuitry to convert an analog signal to a 14-bit digital output. the MAX1144/max1145 easily interface to microprocessors (ps). the data bits can be read either during the conversion in external clock mode or after the conversion in internal clock mode. in addition to a 14-bit adc, the MAX1144/max1145 include an input scaler, an internal digital microcontroller, calibration circuitry, and an internal clock generator. the input scaler for the MAX1144 enables conversion of input signals ranging from 0 to +6v (unipolar input) or 6v (bipolar input). the max1145 accepts 0 to +2.048v (unipolar input) or 2.048v (bipolar input). input range is software selectable. calibration to minimize linearity, offset, and gain errors, the MAX1144/max1145 have on-demand software calibra- tion. initiate calibration by writing a control byte with bit m1 = 0 and bit m0 = 1 (table 1). select internal or exter- nal clock for calibration by setting the int/ ext bit in the control byte. calibrate the MAX1144/max1145 with the same clock mode used for performing conversions. offsets resulting from synchronous noise (such as the conversion clock) are canceled by the MAX1144/ max1145 s calibration circuitry. however, because the magnitude of the offset produced by a synchronous signal depends on the signal s shape, recalibration may be appropriate if the shape or relative timing of the clock, or other digital signals change, as may occur if more than one clock signal or frequency is used. input scaler the MAX1144/max1145 have an input scaler, which allows conversion of true bipolar input voltages while operating from a single 3.3v supply. the input scaler attenuates and shifts the input as necessary to map the external input range to the input range of the internal adc. the MAX1144 analog input range is 0 to +6v (unipolar) or 6v (bipolar). the max1145 analog input 14-bit adcs, 150ksps, 3.3v single supply 8 _______________________________________________________________________________________ bit name description 7 (msb) start the first logic 1 bit after cs goes low defines the beginning of the control byte. 6 uni/ bip 1 = unipolar, 0 = bipolar. selects unipolar or bipolar conversion mode. in unipolar mode, analog input signals from 0 to +6v (MAX1144) or 0 to +vref (max1145) can be converted. in bipolar mode, analog input signals from 6v to +6v (MAX1144) or vref to +vref (max1145) can be converted. 5 int/ ext selects the internal or external conversion clock. 1 = internal, 0 = external. m1 m0 mode 0 0 24 external clocks per conversion (short acquisition mode) 4m1 0 1 start calibration: starts internal calibration 1 0 software power-down mode 3m0 1 1 32 external clocks per conversion (long acquisition mode) 2p2 1p1 0 (lsb) p0 these three bits are stored in a port register and output to pins p2, p1, p0 for use in addressing a mux or pga. these three bits are updated in the port register simultaneously when a new control byte is written. table 1. control byte format figure 1. equivalent input circuit voltage reference bipolar unipolar track s2 s3 s1 = bipolar/unipolar s2, s3 = t/h switch r2 = 7.6k ? (MAX1144) or 2.5k ? (max1145) r3 = 3.9k ? (MAX1144) or infinity (max1145) hold hold t/h out c hold 32pf r1 2.5k ? r2 r3 ain track
range is 0 to +2.048v (unipolar) or 2.048v (bipolar). unipolar and bipolar mode selection is configured with bit 6 of the serial control byte (table 1). figure 1 shows the equivalent input circuit of the MAX1144/max1145. the resistor network on the analog input provides 16.5v fault protection. this circuit limits the current going into or out of the pin to less than 2ma. the overvoltage protection is active even if the device is in a power-down mode, or if av dd = 0. digital interface the digital interface pins consist of shdn , rst , sstrb, dout, sclk, din, and cs . bringing shdn low places the MAX1144/max1145 in its 1.2a shutdown mode. a logic low on rst halts the MAX1144/max1145 opera- tion and returns the part to its power-on-reset state. in external clock mode, sstrb is low and pulses high for one clock cycle at the start of conversion. in internal clock mode, sstrb goes low at the start of the conver- sion, and goes high to indicate that the conversion is finished. the din input accepts control byte data, which is clocked in on each rising edge of sclk. after cs goes low or after a conversion or calibration completes, the first logic 1 clocked into din is interpreted as the start bit, the msb of the 8-bit control byte. the sclk input is the serial-data-transfer clock which clocks data in and out of the MAX1144/max1145. sclk also drives the adc conversion steps in external clock mode (see the internal and external clock modes section). dout is the serial output of the conversion result. dout is updated on the falling edge of sclk. dout is high impedance when cs is high. cs must be low for the MAX1144/max1145 to accept a control byte. the serial interface is disabled when cs is high. user-programmable outputs the MAX1144/max1145 have three user-programma- ble outputs: p0, p1, and p2. the power-on default state for the programmable outputs is zero. these are push- pull cmos outputs suitable for driving a multiplexer, a pga or other signal preconditioning circuitry. bits 0, 1, and 2 of the control byte control the user-programma- ble outputs (tables 1, 2). MAX1144/max1145 14-bit adcs, 150ksps, 3.3v single supply _______________________________________________________________________________________ 9 acquisition conversion idle idle sclk dout a/d state din sstrb cs 4 1812 start m1 m0 p2 p1 p0 15 21 24 b10 b9 b12 b11 b8 b7 b2 b13 msb b0 lsb filled with zeros b1 x x t acq uni/ bip int/ ext figure 2. short acquisition mode (24 clock cycles) external clock output pin programmed through control byte power-on or rst default description p2 bit 2 0 p1 bit 1 0 p0 bit 0 0 user-programmable outputs follow the state of the control byte s three lsbs, and are updated simultaneously when a new control byte is written. outputs are push-pull. in hardware and software shutdown, these outputs are unchanged and remain low impedance. table 2. user-programmable outputs
MAX1144/max1145 the user-programmable outputs are set to zero during power-on reset or when rst goes low. during hardware or software shutdown, p0, p1, and p2 are unchanged and remain low-impedance. starting a conversion start a conversion by clocking a control byte into the device s internal shift register. with cs low, each rising edge on sclk clocks a bit from din into the MAX1144/max1145 s internal shift register. after cs goes low or after a conversion or calibration completes, the first arriving logic 1 is defined as the start bit of the control byte. until this first start bit arrives, any num- ber of logic 0 bits can be clocked into din with no effect. if at any time during acquisition or conversion cs is brought high and then low again, the part is placed into a state where it can recognize a new start bit. if a new start bit occurs before the current conver- sion is complete, the conversion is aborted and a new acquisition is initiated. internal and external clock modes the MAX1144/max1145 use either the external serial clock or the internal clock to perform the successive- approximation conversion. in both clock modes, the external clock shifts data in and out of the MAX1144/max1145. bit 5 (int/ ext ) of the control byte programs the clock mode. external clock in external clock mode, the external clock not only shifts data in and out, but also drives the adc conver- sion steps. in short acquisition mode, sstrb pulses high for one clock period after the seventh falling edge of sclk fol- lowing the start bit. the msb of the conversion is avail- able at dout on the eighth falling edge of sclk (figure 2). 14-bit adcs, 150ksps, 3.3v single supply 10 ______________________________________________________________________________________ sclk dout a/d state din sstrb cs 4 18 start m1 m0 p2 p1 p0 14 29 32 b2 b12 b13 msb b11 b1 xx b0 lsb filled with zeros t acq acquisition conversion idle idle 15 uni/ bip int/ ext figure 3. long acquisition mode (32 clock cycles) external clock t sdv t sstrb t sstrb t str p1 clocked in sstrb sclk cs figure 4. external clock mode sstrb detailed timing
MAX1144/max1145 14-bit adcs, 150ksps, 3.3v single supply ______________________________________________________________________________________ 11 sclk dout din sstrb cs 4 18 start m1 m0 p2 p1 p0 9 21 24 b2 b12 b13 msb b1 xx b0 lsb filled with zeros t acq t conv uni/ bip int/ ext figure 5. internal clock mode timing, short acquisition, bipolar mode in long acquisition mode, sstrb pulses high for one clock period after the 15th falling edge of sclk follow- ing the start bit. the msb of the conversion is available at dout on the 16th falling edge of sclk (figure 3). in external clock mode, sstrb is high impedance when cs is high (figure 4). in external clock mode, cs is normally held low during the entire conversion. if cs goes high during the conversion sclk is ignored until cs goes low. this allows external clock mode to be used with 8-bit bytes. internal clock in internal clock mode, the MAX1144/max1145 generate their own conversion clock. this frees the microprocessor from the burden of running the sar conversion clock, and allows the conversion results to be read back at the processor s convenience, at any clock rate up to 4mhz. sstrb goes low at the start of the conversion and goes high when the conversion is complete. sstrb will be low for a maximum of 7s, during which time sclk should remain low for best noise performance. an inter- nal register stores data when the conversion is in progress. sclk clocks the data out of the internal stor- age register at any time after the conversion is complete. the msb of the conversion is available at dout when sstrb goes high. the subsequent 13 falling edges on sclk shift the remaining bits out of the internal storage register (figure 5). cs does not need to be held low once a conversion is started. p0 clocked in t sstrb t conv t sck t css sstrb sclk note: for best noise performance, keep sclk low during conversion. t csh cs figure 6. internal clock mode sstrb detailed timing
MAX1144/max1145 when internal clock mode is selected, sstrb does not go into a high-impedance state when cs goes high. figure 6 shows the sstrb timing in internal clock mode. in internal clock mode, data can be shifted into the MAX1144/max1145 at clock rates up to 4mhz, pro- vided the minimum acquisition time, t acq , is kept above 1.39s in bipolar mode and 1.67s in unipolar mode. data can be clocked out at 4mhz. output data the output data format is straight binary for unipolar conversions and two s complement in bipolar mode. the msb is shifted out of the MAX1144/max1145 first in both modes. data framing the falling edge of cs does not start a conversion on the MAX1144/max1145. the first logic high clocked into din is interpreted as a start bit and defines the first bit of the control byte. a conversion starts on the falling edge of sclk, after the seventh bit of the control byte (the p1 bit) is clocked into din. the start bit is defined as: the first high bit clocked into din with cs low any- time the converter is idle, e.g. after av dd is applied. the first high bit clocked into din after cs is pulsed high then low. if a falling edge on cs forces a start bit before the con- version or calibration is complete, then the current operation terminates and a new one starts. applications information power-on reset when power is first applied to the MAX1144/max1145, or if rst is pulsed low, the internal calibration registers are set to their default values. the user-programmable registers (p0, p1, and p2) are low, and the device is configured for bipolar mode with internal clocking. calibration periodically calibrate the MAX1144/max1145 to com- pensate for temperature drift and other variations. after any change in ambient temperature more than +10 c, the device should be recalibrated. a 100mv change in supply voltage or any change in the reference voltage should be followed by a calibration. calibration cor- rects for errors in gain, offset, integral nonlinearity, and differential nonlinearity. the MAX1144/max1145 should be calibrated after power-up or after the assertion of reset. make sure the power supplies and the reference voltage have fully settled prior to initiating the calibration sequence. initiate calibration by setting m1 = 0 and m0 = 1 in the control byte. in internal clock mode, sstrb goes low at the beginning of calibration and goes high to signal the end of calibration, approximately 80,000 clock cycles later. in external clock mode, sstrb goes high at the beginning of calibration and goes low to signal the end of calibration. calibration should be performed in the same clock mode that is used for conversions. reference the MAX1144/max1145 require an external reference. the external reference must be bypassed with a 4.7f capacitor. the input impedance at ref is a minimum of 16k ? for dc currents. during conversion, an external reference at ref must deliver up to 150a dc load current and have an output impedance of 10 ? or less. analog input the MAX1144/max1145 use a capacitive dac that provides an inherent track/hold function. drive ain with a source impedance less than 10 ? . any signal condi- tioning circuitry must settle with 14-bit accuracy in less than 500ns. limit the input bandwidth to less than half the sampling frequency to eliminate aliasing. the MAX1144/max1145 have a complex input impedance that varies from unipolar to bipolar mode (figure 1). input range the analog input range in unipolar mode is 0 to +6v for the MAX1144, and 0 to +2.048v for the max1145. in bipolar mode, the analog input can be -6v to +6v for the MAX1144, or -2.048v to +2.048v for the max1145. unipolar or bipolar mode is programmed with the uni/ bip bit of the control byte. when using a reference other than the suggested +2.048v, the full-scale input range varies accordingly. the full-scale input range depends on the voltage at ref and the sampling mode selected (tables 3 and 4). 14-bit adcs, 150ksps, 3.3v single supply 12 ______________________________________________________________________________________ part zero scale full scale MAX1144 0 6 (v ref /2.048) max1145 0 v ref part negative full scale zero scale full scale MAX1144 -6 (v ref /2.048) 0 +6 (v ref /2.048) max1145 -v ref 0+v ref table 3. unipolar full scale and zero scale table 4. bipolar full scale, zero scale, and negative scale
input acquisition and settling clocking in a control byte starts input acquisition. the main capacitor array starts acquiring the input as soon as a start bit is recognized, using the same input range as the previous conversion. if the opposite input range is selected by the second din bit, the part immediately switches to the new sampling mode. acquisition time is one-and-a-half clock cycles shorter when switching from unipolar to bipolar or bipolar to unipolar modes than when continuously converting in the same mode. acquisition can be extended by eight clock cycles by setting m1 = 1 and m0 = 1 (long acquisition mode). the sampling instant in short acquisition completes on the falling edge of the sixth clock cycle after the start bit (figure 2). acquisition is 5 clock cycles in short acquisi- tion mode and 13 clock cycles in long acquisition mode. short acquisition mode is 24 clock cycles per conversion. using the external clock to run the conver- sion process limits unipolar conversion speed to 125ksps instead of 150ksps as in bipolar mode. the input resistance in unipolar mode is larger than that of bipolar mode (figure 1). the rc time constant in unipo- lar mode is larger than that of bipolar mode, reducing the maximum conversion rate in 24 external clock mode. long acquisition mode with external clock allows both unipolar and bipolar sampling of 112ksps as (3.6mhz / 32 clock cycles) by adding eight extra clock cycles to the conversion. most applications require an input buffer amplifier. if the input signal is multiplexed, the input channel should be switched immediately after acquisition, rather than near the end of or after a conversion. this allows more time for the input buffer amplifier to respond to a large step change in input signal. the input amplifier must have a high enough slew rate to complete the required output voltage change before the beginning of the acquisition time. at the beginning of acquisition, the capacitive dac is connected to the amplifier output, causing some output disturbance. ensure that the sampled voltage has set- tled to within the required limits before the end of the acquisition time. if the frequency of interest is low, ain can be bypassed with a large enough capacitor to charge the capacitive dac with very little change in voltage. however, for ac use, ain must be driven by a wideband buffer (at least 10mhz), which must be sta- ble with the dac s capacitive load (in parallel with any ain bypass capacitor used) and also must settle quickly (figure 7). digital noise digital noise can couple to ain and ref. the conver- sion clock (sclk) and other digital signals that are active during input acquisition contribute noise to the conversion result. if the noise signal is synchronous to the sampling interval, an effective input offset is pro- duced. asynchronous signals produce random noise on the input, whose high-frequency components may be aliased into the frequency band of interest. minimize noise by presenting a low impedance (at the frequen- cies contained in the noise signal) at the inputs. this requires bypassing ain to agnd, or buffering the input with an amplifier that has a small-signal bandwidth of several mhz, or preferably both. ain has a bandwidth of about 4mhz. offsets resulting from synchronous noise (such as the conversion clock) are canceled by the MAX1144/ max1145 s calibration scheme. however, because the MAX1144/max1145 14-bit adcs, 150ksps, 3.3v single supply ______________________________________________________________________________________ 13 4 7 6 2 3 in v cc v ee 0.0033 f 0.1 f 0.1 f 100pf 1k ? 1k ? ain figure 7. ain buffer for ac/dc use
MAX1144/max1145 magnitude of the offset produced by a synchronous signal depends on the signal s shape, recalibration may be appropriate if the shape or relative timing of the clock or other digital signals change, which can occur if more than one clock signal or frequency is used. distortion avoid degrading dynamic performance by choosing an amplifier with distortion much less than the MAX1144/max1145 s thd (-90db) at frequencies of interest. if the chosen amplifier has insufficient com- mon-mode rejection, which results in degraded thd performance, use the inverting configuration to elimi- nate errors from common-mode voltage. low tempera- ture-coefficient resistors reduce linearity errors caused by resistance changes due to self-heating. also, to reduce linearity errors due to finite amplifier gain, use an amplifier circuit with sufficient loop gain at the fre- quencies of interest. dc accuracy if dc accuracy is important, choose a buffer with an offset much less than the MAX1144/max1145 s maxi- mum offset (6mv), or whose offset can be trimmed while maintaining good stability over the required tem- perature range. operating modes and serial interfaces the MAX1144/max1145 are fully compatible with microwire and spi/qspi devices. microwire and spi/qspi both transmit a byte and receive a byte at the same time. the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the adc, and two more 8-bit transfers to clock out the 14-bit conversion result). short acquisition mode (24 sclk) configure short acquisition by setting m1 = 0 and m0 = 0. in short acquisition mode, the acquisition time is 5 clock cycles. the total period is 24 clock cycles per conversion. long acquisition mode (32 sclk) configure long acquisition by setting m1 = 1 and m0 = 1. in long acquisition mode, the acquisition time is 13 clock cycles. the total period is 32 clock cycles per conversion. calibration mode a calibration is initiated through the serial interface by setting m1 = 0 and m0 = 1. calibration can be done in either internal or external clock mode, though it is desir- able that the part be calibrated in the same mode in which it will be used to do conversions. the part remains in calibration mode for approximately 80,000 clock cycles unless the calibration is aborted. calibr- ation is halted if rst or shdn goes low, or if a valid start condition occurs. software shutdown a software power-down is initiated by setting m1 = 1 and m0 = 0. after the conversion completes, the part shuts down. it reawakens upon receiving a new start bit. conversions initiated with m1 = 1 and m0 = 0 (shut- down) use the acquisition mode selected for the previ- ous conversion. shutdown mode the MAX1144/max1145 may be shut down by pulling shdn low or by asserting software shutdown. in addi- tion to lowering power dissipation to 4w, considerable power can be saved by shutting down the conv- erter for short periods between conversions. there is no need to perform a calibration after the converter has been shut down unless the time in shutdown is long enough that the supply voltage or ambient temperature may have changed. supplies, layout, grounding, and bypassing for best system performance, use separate analog and digital ground planes. the two ground planes should be tied together at the MAX1144/max1145. use pin 3 and pin 14 as the primary agnd and dgnd, respec- tively. if the analog and digital supplies come from the same source, isolate the digital supply from the analog with a low-value resistor (10 ? ). the MAX1144/max1145 are not sensitive to the order of av dd and dv dd sequencing. either supply can be present in the absence of the other. do not apply an external reference voltage until after both av dd and dv dd are present. be sure that digital return currents do not pass through the analog ground. all return-current paths must be low impedance. a 5ma current flowing through a pc board ground trace impedance of only 0.05 ? creates an error voltage of about 250v, or about 0.5lsbs error with a 4v full-scale system. the board layout should ensure that digital and analog signal lines are kept separate. do not run analog and digital lines parallel to one another. if you must cross one with the other, do so at right angles. the adc is sensitive to high-frequency noise on the av dd power supply. bypass this supply to the analog ground plane with 0.1f. if the main supply is not ade- quately bypassed, add an additional 1f or 10f low- esr capacitor in parallel with the primary bypass capacitor. 14-bit adcs, 150ksps, 3.3v single supply 14 ______________________________________________________________________________________
transfer function figures 8 and 9 show the max1145 s transfer functions. in unipolar mode the output data is in binary format and in bipolar mode it is in two s complement format. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. inl for the MAX1144/max1145 is measured using the end- point method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of full- scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the adc s resolution (n- bits): snr = (6.02 x n + 1.76) db in reality, there are other noise sources besides quanti- zation noise, including thermal noise, reference noise, clock jitter, etc. therefore, snr is calculated by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamen- tal, the first five harmonics, and the dc offset. MAX1144/max1145 14-bit adcs, 150ksps, 3.3v single supply ______________________________________________________________________________________ 15 output code full-scale transition 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 12 3 0 fs fs - 3/2lsb fs = 2.048v 1lsb = input voltage (lsbs) 16384 fs figure 8. max1145 unipolar transfer function, 2.048v = full scale 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 -fs 0 input voltage (lsbs) +fs - 1lsb +fs = +2.048v -fs = -2.048v 1lsb = 16384 output code 4.096v figure 9. max1145 bipolar transfer function, 4.096v = full scale
MAX1144/max1145 signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency s rms amplitude to the rms equivalent of all other adc output signals: sinad (db) = 20 x log (signal rms / noise rms ) total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v1 is the fundamental amplitude, and v2 through v5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest distortion component. thd vvvv v = +++ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log 14-bit adcs, 150ksps, 3.3v single supply 16 ______________________________________________________________________________________ functional diagram cref av dd agnd ref cs rst ain dv dd dgnd sclk din analog timing control input scaling network serial output port serial input port memory calibration engine clock generator control dac comparator p2 sstrb dout p1 p0 shdn MAX1144 max1145
MAX1144/max1145 14-bit adcs, 150ksps, 3.3v single supply ______________________________________________________________________________________ 17 ordering information (continued) part temp range pin- package inl (lsb) max1145 acap 0 c to +70 c 20 ssop 1 max1145bcap 0 c to +70 c 20 ssop 2 max1145aeap -40 c to +85 c 20 ssop 1 max1145beap -40 c to +85 c 20 ssop 2 MAX1144/ max1145 ain av dd dv dd ref 2.048v 4.7 f 1 f 0.1 f 0.1 f cref agnd cs sclk din dout rst sstrb i/o mc68hcxx sclk mosi miso i/o dgnd 3.3v 3.3v shdn typical application circuit chip information transistor count: 21,807 process: bicmos
MAX1144/max1145 14-bit adcs, 150ksps, 3.3v single supply maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. ssop.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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